This disclosure generally relates to a system and technique for a processor having a staged execution pipeline.
For purposes of reducing latency in its processing, a processor may employ pipelining. The pipelining increases processor efficiency by causing the processor to process multiple instructions at the same time. In this manner, the processor typically processes a given instruction in multiple stages that extend over several processing cycles. With pipelining, the processor processes different stages of multiple instructions at the same time, which allows the processor to execute more instructions in a relatively shorter period of time, as compared to the processor completely processing each instruction before beginning the processing of the next instruction. As an example of pipelining, the processor may fetch a first instruction, while concurrently executing a second instruction and performing a memory access related to a third instruction.